View LTC4121-42-15_8232833.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 typical a pplica t ion fea t ures descrip t ion 40v 400ma synchronous step-down battery charger the lt c ? 4121 is a 400ma constant-current/constant- voltage (cc/cv) synchronous step-down battery charger . in addition to cc/cv operation, the ltc4121 regulates its input voltage to a programmable percentage of the input open-circuit voltage . this technique maintains maximum power transfer with high impedance input sources such as solar panels. an external resistor programs the charge current up to 400ma. the ltc4121-4.2 is suitable for charging li-ion/ polymer batteries, while the programmable float voltage of the ltc4121 is suitable for several battery chemistries. the ltc4121 and ltc4121-4.2 include an accurate run pin threshold , low voltage battery preconditioning and bad battery fault detection , timer termination, auto-recharge, and ntc temperature qualified charging . the fault pin provides an indication of bad battery or temperature faults . once charging is terminated, the ltc4121 signals end-of- charge via the chrg pin, and enters a low current sleep mode. an auto-restart feature starts a new charging cycle if the battery voltage drops by 2.2%. ltc4121 efficiency vs v in at v float = 8.4v a pplica t ions n wide input voltage range: 4.4v to 40v n temperature compensated input voltage regulation for maximum power point tracking (mppt) n adjustable float voltage 3.5v to 18v (ltc4121) n fixed 4.2v float voltage option (ltc4121-4.2) n high efficiency: up to 95% n 50ma to 400ma programmable charge current n 1% feedback voltage accuracy n programmable 5% accurate charge current n thermally enhanced, low profile (0.75mm) 16-lead (3mm 3mm) qfn package n handheld instruments n solar powered devices n industrial/military sensors and devices l, lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. intv cc boost sw chgsns bat fb fbg in run mppt prog ltc4121 gnd 10k 10f r prog v in v bat + 200mv to 40v 22nf slf6025t-470mr48 2.2f freq + 22f 1.96m 787k 4121 ta01a li-ion + ? high efficiency, wide input voltage range charging with ltc4121 v in (v) 5 87 efficiency (%) 89 91 93 95 97 10 15 20 4121 ta01b 25 30 35 40 200ma, r prog = 6.04k 400ma, r prog = 3.01k v bat = 8.3v lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
2 a bsolu t e maxi m u m r a t ings in , run , chrg , fa u lt , mppt ................... C0. 3v to 4 3v boost ................................... v sw C 0. 3v to (v sw + 6v ) sw ( dc ) ........................................ C0. 3v to (v in + 0. 3v ) sw (pulsed < 100ns ) ...................... C 1. 5v to (v in + 1. 5v ) chgsns , bat , fb / batsns , fbg ................ C 0. 3v to 18v freq , ntc, prog , intv cc .......................... C0. 3v to 6v i chgsns , i bat ..................................................... 60 0ma (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc4121eud#pbf ltc4121eud#trpbf lghc 16-lead (3mm 3mm) plastic qfn C40c to 125c ltc4121iud#pbf ltc4121iud#trpbf lghc 16-lead (3mm 3mm) plastic qfn C40c to 125c ltc4121eud-4.2#pbf ltc4121eud-4.2#trpbf lgmv 16-lead (3mm 3mm) plastic qfn C40c to 125c ltc4121iud-4.2#pbf ltc4121iud-4.2#trpbf lgmv 16-lead (3mm 3mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking , go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc4121 ltc4121-4.2 16 15 14 13 5 6 7 8 top view gnd ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1intv cc boost in sw ntc fbg fb bat run fault chrg prog gnd mppt freq chgsns t jmax = 125c, ja = 54c/w exposed pad (pin 17) is gnd, must be soldered to pcb to obtain ja 16 15 14 13 5 6 7 8 top view gnd ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1intv cc boost in sw ntc nc batsns bat run fault chrg prog gnd mppt freq chgsns t jmax = 125c, ja = 54c/w exposed pad (pin 17) is gnd, must be soldered to pcb to obtain ja p in c on f igura t ion i chrg , i fa u lt , ........................................................ 5ma i fb , i fbg ( lt c4121 ) ................................................. 5m a i batsns ( lt c4121 -4 .2) ........................................... 5m a i intvcc .................................................................. C 5ma o perating junction temperature range ( note 2 ) .................................................. C 40 c to 125c storage temperature range .................... C 65 c to 150 ltc4121 options part number float voltage ltc4121 programmable ltc4121-4.2 4.2v fixed lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = v run = 15v, v chgsns = v bat = 4v, r prog = 3.01k, v fb = 2.29v (ltc4121), v batsns = 4v (ltc4121-4.2). current into a pin is positive out of a pin is negative. (note 2) symbol parameter conditions min typ max units operating input supply range l 4.4 40 v battery voltage range ltc4121 (note 3) 0 18 v ltc4121-4.2 0 4.2 v i in dc supply current switching: freq = gnd 3.5 ma standby mode: (note 4) l 142 260 a sleep mode: (note 4) ltc4121-4.2: v batsns = 4.4v ltc4121: v fb = 2.51v (note 6) l 60 110 a disabled mode : v sd < v run < v en (note 4) l 37 80 a shutdown mode: (note 4) l 20 40 a ?v duvlo differential undervoltage lockout v in C v bat falling, v in = 5v (ltc4121) v in C v batsns falling, v in = 5v (ltc4121-4.2) l 20 80 160 mv hysteresis v in C v bat rising, v in = 5v (ltc4121) v in C v batsns rising, v in = 5v (ltc4121-4.2) 115 mv uv intvcc intv cc undervoltage lockout intv cc rising, v in = intv cc + 100mv l 4.00 4.15 4.26 v hysteresis intv cc falling 220 mv intv cc regulated voltage l 4.14 4.24 4.29 v intv cc load regulation intv cc = 0ma to C5ma (note 5) 1.7 % battery charger i bat bat standby current standby mode (ltc4121) (notes 4, 8, 9) standby mode (ltc4121-4.2) (notes 4, 8, 9) l l 2.5 50 4 .5 1000 a na bat shutdown current shutdown mode (ltc4121) (notes 4, 8, 9) shutdown mode (ltc4121-4.2) (notes 4, 8, 9) l l 1100 10 2000 1000 na na i batsns batsns standby current (ltc4121-4.2) standby mode (notes 4, 8, 9) l 5.4 10 a batsns shutdown current (ltc4121-4.2) shutdown mode (notes 4, 8, 9) l 1100 2000 na i fb feedback pin bias current (ltc4121) v fb = 2.5v (note 6) l 25 60 na i fbg_leak feedback ground leakage current (ltc4121) shutdown mode (note 4) l 1 a r fbg feedback ground return resistance (ltc4121) l 1000 2000 v fb(reg) feedback pin regulation voltage (ltc4121) (note 6) 2.393 2.400 2.407 v l 2.370 2.418 v v float regulated float voltage (ltc4121-4.2) 4.188 4.200 4.212 v l 4.148 4.231 v i chg battery charge current r prog = 3.01k l 383 402 421 ma r prog = 24.3k l 45 50 55 ma v rchg battery recharge threshold v fb falling relative to v fb(reg) (ltc4121) l C38 C49 C62 mv v rchg_4.2 v batsns falling relative to v float (ltc4121-4.2) l C70 C93 C114 mv h prog ratio of bat current to prog current v trkl < v fb < v fb(reg) (ltc4121), v trkl_42 < v batsns < v float (ltc4121-4.2) 988 ma/ma v prog prog pin servo voltage l 1.206 1.227 1.248 v r sns chgsns-bat sense resistor i bat = C100ma 300 m lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = v run = 15v, v chgsns = v bat = 4v, r prog = 3.01k, v fb = 2.29v (ltc4121), v batsns = 4v (ltc4121-4.2). current into a pin is positive out of a pin is negative. (note 2) symbol parameter conditions min typ max units i lowbat low battery linear charge current v fb < v trkl , v bat = 2.6v (ltc4121) (note 6) 6 9 16 ma v batsns < v trkl_4.2 , v bat = 2.6v (ltc4121-4.2) v lowbat low battery threshold voltage v bat rising (ltc4121) v batsns rising (ltc4121-4.2) l 2.15 2.21 2. 28 v hysteresis 147 mv i trkl switch mode trickle charge current v lowbat < v bat , v fb < v trkl (ltc4121) (note 6) i chg /10 ma v lowbat < v batsns < v trkl_42 (ltc4121-4.2) prog pin servo voltage in trickle charge v lowbat < v bat , v fb > v trkl (ltc4121) (note 6) 122 mv v lowbat < v batsns < v trkl_42 (ltc4121-4.2) v trkl trickle charge threshold (ltc4121) v fb rising (note 6) l 1.65 1.68 1.71 v hysteresis (ltc4121) v fb falling (note 6) 50 mv v trkl_4.2 trickle charge threshold (ltc4121-4.2) v batsns rising l 2.86 2.91 2.98 v hysteresis (ltc4121-4.2) v batsns falling 88 mv h c/10 end of charge indication current ratio (note 7) 0.1 ma/ma safety timer termination period 1.3 2.0 2.8 hrs bad battery termination timeout 19 30 42 min switcher f osc switching frequency freq = intv cc l 1.0 1.5 2.0 mhz freq = gnd l 0.5 0.75 1.0 mhz t min_on minimum controllable on-time 120 ns duty cycle maximum 94 % top switch r dson i sw = C100ma 0.8 bottom switch r dson i sw = 100ma 0.5 i peak peak inductor current limit measured across r sns with a 15h inductor in series with r sns (note 10) 585 1050 1250 ma i sw switch pin current (note 9) in open-circuit, v bat = v sw = 4.2v (ltc4121-4.2) l 7 15 a in open-circuit, v bat = v sw = 8.4v (ltc4121) l 15 30 a status pins fault, chrg pin output voltage low i = 2ma 550 mv pin leakage current v = 43v, pin high-impedance 0 1 a ntc cold temperature v ntc / v intvcc fault rising v ntc threshold l 73 74 75 %intv cc falling v ntc threshold 72 %intv cc hot temperature v ntc / v intvcc fault falling v ntc threshold l 35.5 36.5 37.5 %intv cc rising v ntc threshold 37.5 %intv cc ntc disable voltage falling v ntc threshold l 1 2 3 %intv cc rising v ntc threshold 3 %intv cc ntc input leakage current v ntc = v intvcc C50 50 na lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
5 symbol parameter conditions min typ max units run v en enable threshold v run rising l 2.35 2.45 2.55 v hysteresis v run falling 200 mv run pin input current v run = 40v 0.01 0.1 a v sd shutdown threshold v run falling l 0.4 1.2 v hysteresis 220 mv freq freq pin input low l 0.4 v freq pin input high l 3.6 v freq pin input current 0 < v freq < v intvcc 1 a mppt i mppt mppt pin leakage current v mppt = 4.2v l 15 1000 na t mp mppt sample period period between charger disabled events 28 s pw mp mppt sample pulse width charger disabled pulse width 36 ms k f internal divider gain internal dac voltage as a ratio to v in 0.098 0.1 0.102 v/v v mp(os) mppt error amp gain offset v mppt C v dac , i bat = 50%? i chg 10 C45 C100 mv e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = v run = 15v, v chgsns = v bat = 4v, r prog = 3.01k, v fb = 2.29v (ltc4121), v batsns = 4v (ltc4121-4.2). current into a pin is positive out of a pin is negative. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4121 is tested under pulsed load conditions such that t j t a . the ltc4121e is guaranteed to meet performance specifications for junction temperatures from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc4121i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. note 3: if a battery voltage greater than 11v can be hot plugged to the ltc4121 a reverse blocking diode is required in series with the bat pin to prevent large inrush current into the low impedance bat pin. note 4: standby mode occurs when the ltc4121/ltc4121-4.2 stops switching due to an ntc fault, mppt pause, or when the charge current has dropped low enough to enter burst mode operation. disabled mode occurs when v run is between v sd and v en . shutdown mode occurs when v run is below v sd or when the differential undervoltage lockout is engaged. sleep mode occurs after a timeout while the battery voltage remains above the v rchg or v rchg_42 threshold. note 5: the internal supply intv cc should only be used for the ntc divider, it should not be used for any other loads note 6: for the ltc4121, the fb pin is measured with a resistance of 588k in series with the pin. note 7: h c/10 is expressed as a fraction of measured full charge current as measured at the prog pin voltage when the chrg pin de-asserts. note 8: in an application circuit with an inductor connected from sw to chgsns, the total battery leakage current when disabled is the sum of i batsns and i sw (ltc4121-4.2) or i bat and i fbg_leak and i sw (ltc4121). note 9: when no supply is present at in, the sw powers in through the body diode of the top side switch. this may cause additional sw pin current depending on the load present at in. note 10: guaranteed by design and/or correlation to static test. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
6 typical p er f or m ance c harac t eris t ics in pin sleep/disabled/shutdown current vs temperature bat pin sleep/shutdown current vs temperature feedback pin standby or sleep/ disabled current vs temperature batsns pin sleep/standby or shutdown/disabled current vs temperature bat pin standby/sleep/shutdown current vs temperature typical v fb(reg) vs temperature typical v float vs temperature in pin standby current vs temperature temperature (c) ?40 4.15 v float (v) 4.16 4.17 4.23 4.22 4.21 4.20 4.18 4.19 4.25 4.24 ?25 ?10 5 20 4121 g02 35 50 65 80 95 110 125 3 units tested ltc4121-4.2 v in = 5v high limit dut1 v float dut2 v float dut3 v float low limit temperature (c) ?40 0 i in (a) 60 50 40 30 10 20 90 80 70 ?25 ?10 5 20 4121 g04 35 50 65 80 95 110 125 sleep dis sd v in = 15v temperature (c) ?40 2.36 v fb(reg) (v) 2.37 2.38 2.41 2.40 2.39 2.43 2.42 ?25 ?10 5 20 4121 g01 35 50 65 80 95 110 125 4 units tested high limit dut1 dut2 dut3 dut4 low limit ltc4121 v in = 15v temperature (c) ?40 80 i in (a) 90 100 160 150 140 130 110 120 180 170 ?25 ?10 5 20 4121 g03 35 50 65 80 95 110 125 standby freq high standby freq low v in = 15v temperature (c) ?40 0 i bat (a) 6 5 4 3 1 2 8 7 ?25 ?10 5 20 4121 g05 35 50 65 80 95 110 125 sleep v bat = 8.4v sleep v bat = 4.2v shutdown v bat = 8.4v shutdown v bat = 4.2v ltc4121 temperature (c) ?40 0 i fb (na) 50 40 30 10 20 60 ?25 ?10 5 20 4121 g06 35 50 65 80 95 110 125 standby v fb = 2.51v sleep/dis v fb = 2.51v ltc4121 temperature (c) ?40 0 i batsns (a) 6 5 4 3 1 2 8 7 ?25 ?10 5 20 4121 g07 35 50 65 80 95 110 125 sleep/standby v batsns = 4.25v shutdown/dis v batsns = 4.25v ltc4121-4.2 temperature (c) ?40 0 i bat (na) 600 500 400 300 100 200 800 700 ?25 ?10 5 20 4121 g08 35 50 65 80 95 110 125 shutdown v bat = 4.25v standby v bat = 4.25v sleep v bat = 4.25v ltc4121-4.2 typical r sns current limit i peak vs temperature temperature (c) ?40 920 i peak (ma) 1080 1040 1020 1000 940 960 980 1120 1100 ?25 ?10 5 20 4121 g09 35 50 65 80 95 110 125 dut1 dut2 dut3 3 units tested t a = 25c, unless otherwise noted. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
7 typical p er f or m ance c harac t eris t ics typical burst mode waveforms in pin shutdown current vs input voltage burst mode trigger current typical battery charge current vs temperature typical solar charging cycle efficiency vs i b at i bat (ma) 0 40 efficiency (%) 70 60 50 100 80 90 100 4121 g10 200 300 400 v in = 9v v in = 14v v in = 19v v in = 24v ltc4121-42 v bat = 4.2v freq = low l sw = slf12575t-470m2r7 temperature (c) ?40 0 i chg (ma) 150 100 250 200 50 450 350 300 400 ?25 4121 g11 ?10 5 20 35 50 65 80 95 110 125 v in = 15v v bat = 3.8v r prog = 3.01k r prog = 6.04k r prog = 12.1k r prog = 24.3k time (hr) 0 0 battery current (ma) v bat , v chrg (v) 150 100 250 200 50 450 350 300 400 0 1.5 1.0 2.5 2.0 0.5 4.5 3.5 3.0 4.0 0.5 4121 g12 1 1.5 2 2.5 3 3.5 bat = 500mahr l sw = tdk slf7045 47h r fb1 = 732k, r fb2 = 976k r prog = 3.01k v chrg i bat v bat v in (v) 5 0 i in (a) 30 20 50 40 10 80 70 60 10 4121 g15 15 20 25 30 35 40 shutdown 130c shutdown 25c shutdown ?45c in pin disabled current vs input voltage v in (v) 5 0 i in (a) 30 20 50 40 10 80 70 60 10 4121 g16 15 20 25 30 35 40 disabled 130c disabled 25c disabled ?45c v in (v) 5 0 i bat (ma) 30 20 50 40 10 100 70 60 90 80 10 4121 g13 15 20 25 30 35 40 r prog = 3.01k r prog = 6.04k v sw 5v/div v prog 200mv/div i sw 200ma/div 4121 g14 4s/div v in = 15v v bat = 4.2v i bat = 38ma freq = gnd t a = 25c, unless otherwise noted. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
8 p in func t ions intv cc ( pin 1): internal low drop out (ldo) regulator output pin. this pin is the output of an internal linear regulator that generates the internal intv cc supply from in. it also supplies power to the switch gate drivers and the low battery linear charge current i lowbat . connect a 2.2f low esr capacitor from intv cc to gnd. do not place any external load on intv cc other than the ntc bias network . when the run pin is above v en , and intv cc rises above the uvlo threshold and in rises above bat by ?v duvlo and its hysteresis, the charger is enabled. boost ( pin 2): boosted supply pin. connect a 22nf boost capacitor from this pin to the sw pin. in ( pin 3): positive input power supply. decouple to gnd with a 10f or larger low esr capacitor. the input supply impedance and the input decoupling capacitor form an rc network that must settle during the mppt sample pulse width of about 36ms. this allows the ltc4121 to sample the open-circuit voltage. sw ( pin 4): switch pin. the sw pin delivers power from in to bat via the step-down switching regulator . an in - ductor should be connected from sw to chgsns. see the applications information section for a discussion of inductor selection. gnd (pin 5, exposed pad pin 17): ground pin. connect to exposed pad. the exposed pad must be soldered to pcb gnd to provide a low electrical and thermal impedance connection to ground. mppt ( pin 6): maximum power point tracking pin. this pin is used to program an input voltage regulation loop. connect an external resistive divider from v in to mppt to gnd. this divider programs the maximum power point voltage as percentage of the input open-circuit voltage . for more information on programming the mppt resis - tive divider refer to the application information section. if the input voltage regulation feature is not used , connect mppt to either intv cc or in with a minimum 10k resistor. keep parasitic capacitance at the mppt pin to a minimum as capacitance at this pin forms a pole that may interfere with switching regulator stability. freq ( pin 7): step-down regulator switching frequency select input pin. connect to intv cc to select a 1.5mhz switching frequency or gnd to select a 750khz switching frequency. do not float. chgsns ( pin 8): battery charge current sense pin. an internal current sense resistor between chgsns and bat pins monitors battery charge current . an inductor should be connected from sw to chgsns. in pin switching current vs input voltage in pin sleep current vs input voltage in pin standby current vs input voltage v in (v) 5 0 i in(switching) (ma) 2 4 3 1 7 6 5 10 4121 g17 15 20 25 30 35 40 freq = intv cc i bat = 0 freq = gnd 130c 25c ?45c v in (v) 5 0 i iin (a) 40 20 80 60 140 120 100 10 4121 g18 15 20 25 30 35 40 sleep 130c sleep 25c sleep ?45c v in (v) 5 80 i iin (a) 100 90 120 110 180 170 130 150 140 160 10 4121 g19 15 20 25 30 35 40 standby freq high 25c standby freq low 25c typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
9 p in func t ions bat ( pin 9): battery output pin. battery charge current is delivered from this pin through the internal charge current sense resistor . in low battery conditions a small linear charge current, i lowbat , is sourced from this pin to precondition the battery . decouple the bat pin with a low esr 22f ceramic capacitor to gnd. batsns ( pin 10 , ltc4121-4.2 only): battery voltage sense pin . for proper operation, this pin must always be connected physically close to the positive battery terminal . fb ( pin 10 , ltc4121 only): battery voltage feedback reference pin. the charge function operates to achieve a final float voltage of 2.4v at this pin. battery float voltage is programmed using a resistive divider from bat to fb to fbg, and can be programmed from 3.5v up to 18v. the feedback pin input bias current, i fb , is 25na. using a resistive divider with a thevenin equivalent resistance of 588k compensates for input bias current error. fbg ( pin 11 , ltc4121 only): feedback ground pin. this pin disconnects the external fb divider load from the battery when it is not needed . when sensing the battery voltage this pin presents a low resistance, r fbg , to gnd. when in disabled or shutdown modes this pin is high impedance. ntc ( pin 12 ): input to the negative temperature coefficient thermistor monitoring circuit . the ntc pin connects to a negative temperature coefficient thermistor which is typically co-packaged with the battery to determine if the battery is too hot or too cold to charge . if the batterys temperature is out of range, the ltc4121 enters standby mode and charging is paused until the battery tempera - ture re-enters the valid range. a low drift bias resistor is required from intv cc to ntc and a thermistor is required from ntc to gnd. tie the ntc pin to gnd, and omit the ntc resistive divider to disable ntc qualified charging if ntc functionality is not required. prog ( pin 13): charge current program and charge current monitor pin. connect a 1% resistor between 3.01k (400ma) and 24.3k (50ma) from prog to ground to program the charge current. while in constant-current mode, this pin regulates to 1.227v. the voltage at this pin represents the average charge current using the following formula: i chg = h prog ? v prog r prog where h prog is typically 988. keep parasitic capacitance on the prog pin to a minimum. if monitoring charge cur - rent via the voltage at the prog pin add a series resistor of at least 2k to isolate stray capacitance from this node. chrg ( pin 14): open-drain charge status output pin. typically pulled up through a resistor to a reference voltage, the chrg pin indicates the status of the battery charger. the pin can be pulled up to voltages as high as in when disabled, and can sink currents up to 5ma when enabled. when the battery is being charged, the chrg pin is pulled low. when the termination timer expires or the charge current drops below 10% of the programmed value, the chrg pin is forced to a high impedance state. fault ( pin 15 ): open-drain fault status output pin. typi - cally pulled up through a resistor to a reference voltage, this status pin indicates fault conditions during a charge cycle. the pin can be pulled up to voltages as high as in when disabled, and can sink currents up to 5ma when enabled. an ntc temperature fault causes this pin to be pulled low. a bad battery fault also causes this pin to be pulled low . if no fault conditions exist, the fault pin remains high impedance. run ( pin 16): run pin. when run is pulled below v en and its hysteresis, the device is disabled. in disabled mode, battery charge current is zero and the chrg and fault pins assume high impedance states. if the voltage at run is pulled below v sd , the device is in shutdown mode. when the voltage at the run pin rises above v en , the intv cc ldo turns on. when the intv cc ldo rises above its uvlo threshold the charger is enabled . the run pin should be tied to a resistive divider from v in to program the input voltage at which charging is enabled . do not float the run pin. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
10 b lock diagra m in intv cc ltc4121 enable d1 c in 10f + + + 4121 f01 boost run c bst 22nf l sw 22h sw mppt ntc fault freq + ? 2.45v + ? 0.9 + ? in-80mv bat shutdown duvlc pwm intv cc ldo enable chgsns bat gnd prog enable chrg cntrl intv cc i th ntc in intv cc intv cc gm enable lowbat hot cold disable + ? 2.21v bat + ? + ? i mppt r mppt1 r mppt2 9r r k r ? v in k f ? v in dac intv cc t mp k f ? v in +v mp(os) intv cc + ? intv cc intv cc c-ea v-ea 588k + ? r fb1 r fb2 r prog 3.01k c bat 22f fb fbg r sns 0.3 v fb(reg) 10k r nom 10k t dz c intvcc 2.2f r run1 r run2 figure 1. block diagram lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
11 b lock diagra m figure 2. ltc4121-4.2 batsns connections 4121 f02 chgsns bat prog lowbat + ? 2.21v batsns duvlo ltc4121-4.2 + ? intv cc + ? intv cc c-ea v-ea 588k + ? c bat 22f li-ion batsns r sns 0.3 2.4v dz batsns in-80mv enable i th mppt in intv cc gm + ? + ? i mppt r mppt1 r mppt2 9r r k r ? v in k f ? v in v in dac intv cc t mp k f ? v in +v mp(os) lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
12 o pera t ion overview the ltc4121 is a synchronous step-down ( buck) monolithic battery charger with maximum power-point tracking ( mppt ) control of the source voltage . the ltc4121/ ltc4121-4. 2 serves as a constant-current / constant-voltage battery charger with the following built-in charger functions: programmable charge current, battery precondition with ? hour timeout, precision shutdown/ run control , ntc thermal protection, a 2- hour safety ter - mination timer, and automatic recharge. the ltc4121/ ltc4121-4. 2 also provides output pins to indicate state of charge and fault status. maximum power point tracking the ltc4121 employs an mppt algorithm that compares a stored open-circuit input voltage measurement against the instantaneous input voltage while charging. the ltc4121 automatically reduces the charge current if the input voltage falls below the user defined percentage of the open-circuit voltage. this algorithm lets the ltc4121 optimize power transfer for a variety of different input sources including first order temperature compensation of a solar panel. the ltc4121 periodically pauses charging to measure the open-circuit voltage allowing the ltc4121 to track fluctuations in the available power . about once every 30 seconds the ltc4121 pauses charging and waits about 36ms ( pw mp ) for the input voltage to recover to its open-circuit potential . at the end of this recovery time, the ltc4121 samples the input voltage divided by 10 (1/ k f ), and stores this value on a digital to analog converter (dac). when charging resumes, the dac voltage is com - pared against the mppt pin voltage that is programmed with a resistive divider . if the mppt voltage falls below the dac voltage, the charge current is reduced to regulate the input voltage at that level. this regulation loop serves to maintain the input voltage at or above a user defined level that corresponds to the peak power available from the applied source. a timing diagram illustrating the sampling of the open- circuit voltage is shown below . the charge current drops to zero and the ltc4121 waits pw mp and then samples the open-circuit voltage . when charging resumes the input voltage collapses if the source cannot support the demanded charge current. when the input voltage drops to v mp , the charge current is reduced so as to maintain v in at v mp . figure 3. mppt timing diagram 4121 f03 time time t mp = 30s pw mp = 36ms sample v in(oc) store in dac: 23s v in recovers pause charger i chg v oc v in i bat v mp connect the mppt pin to a resistive input voltage divider , as shown in figure 4, to program the fraction (k r ) of the input voltage where the input voltage regulation loop reduces available charge current. the ltc4121 reduces charge current if the mppt pin voltage falls below the fixed fraction (k f ) of the open-circuit voltage (v oc ). the ratio of (k f /k r ) defines the maximum power voltage (v mp ) of the applied power source as a ratio to the open-circuit voltage (v oc ) following the relation: v mp v oc = k f k r = 0.1 k r = 0.1 ? r mppt1 + r mppt2 ( ) r mppt2 where the mppt pin resistive divider gain is k r = r mppt2 / (r mppt1 + r mppt2 ). these equations can be rearranged to solve for r mppt2 in terms of k f (0.1) and the maximum power voltage divided by the open circuit voltage , (v mp /v oc ) as: r mppt2 = 0.1 v mp v oc ? ? ? ? ? ? ? 0.1 ? r mppt 1 this function serves to maintain the input voltage at or above the peak power voltage while the ltc4121 charges a battery. because mppt operation involves large changes of input voltage, it is important to ensure that the programmed maximum power voltage does not violate minimum input operating conditions : 4.4v or 160mv above the battery voltage, whichever is higher. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
13 o pera t ion when no power source is applied to v in , for example when using a solar panel source and the panel is in the dark , the mppt pin divider drains power from the battery through the body diode of the top side switch of the switching regula - tor. to eliminate this leakage path, the mppt divider may be connected to the anode of the schottky diode that is in series with the panel , for examples see figures 1, 9, or 10. for example, consider charging a battery from a source with an open-circuit voltage of 30v and a source impedance of 120. this resistive supply has a short circuit current of 250ma, and the peak available power of 1.875w oc - curs with a load of 125ma at 50% of v oc . to program the ltc4120 to optimize the available power for this source simply program v mp /v oc to 50% by selecting the mppt resistive divider gain k r = 0.2. this is obtained with a resis - tive divider as shown in figure 4 with r mppt2 = r mppt1 /4. with standard 1% resistors this is approximated with r mppt1 = 402k, and r mppt2 = 100k. if the mppt pin sees excess capacitance to gnd , this may affect switching regulator stability. in such cases, one may optionally add a 50pf to 150pf lead capacitor (c mppt ) as shown in figure 4. the sampling of v oc is done at an extremely low duty cycle so as to have minimum impact on the average charge current. the time between sample events, t mp , is typically about 30 seconds, with an idle time, pw mp , of about 36ms to allow the source to recover to its open-circuit voltage through the time constant associ - ated with the input decoupling capacitor c in . the time constant for the source to recover to its open-circuit voltage must be kept below the idle period. limit the input capacitor to 10f to avoid increasing the source recovery time. programming the battery float voltage for the ltc4121, the battery float voltage is programmed by placing a resistive divider from the battery to fb and fbg as shown in figure 5. the battery float voltage is programmable anywhere from 3.5v up to 18v. the pro - grammable battery float voltage , v float , is then governed by the following equation: v float = v fb(reg) ? r fb1 + r fb2 ( ) r fb2 where v fb(reg) is typically 2.4v. due to the input bias current (i fb ) of the voltage error amp (v-ea), care must also be taken to select the thevenin equivalent resistance of r fb1 //r fb2 close to 588k. start by calculating r fb1 to satisfy the following relations: r fb1 = v float ? 588k v fb(reg) find the closest 0.1% or 1% resistor to the calculated value. with r fb1 calculate: r fb2 = v fb(reg) ? r fb1 v float ? v fb(reg) ? 1000 ? where 1000 represent the typical value of r fbg . this is the resistance of the fbg pin which serves as the ground return for the battery float voltage divider. once r fb1 and r fb2 are selected re-calculate the value of v float obtained with the resistors available. if the error figure 4. mppt resistive divider figure 5. programming the float voltage with ltc4121 4121 f05 bat 22f r fb1 v float r fb2 li-ion + fb fbg enable i fb ltc4121 4121 f04 in r mppt1 c mppt (optional) r mppt2 i mppt mppt gnd ltc4121 lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
14 o pera t ion is too large substitute another standard resistor value for r fb1 and recalculate r fb2 . repeat until the float voltage error is acceptable. table 1 and table 2 below list recommended standard 0 .1% and 1% resistor values for common battery float voltages. table 1. recommended 0.1% resistors for common v float v float (v) r fb1 (k) r fb2 (k) typical error (%) 3.6 887 1780 C0.13 4.1 1010 1420 0.15 4.2 1010 1350 C0.13 7.2 1800 898 0.08 8.2 2000 825 0.14 8.4 2050 816 0.27 table 2 recommended 1% resistors for common v float v float (v) r fb1 (k) r fb2 (k) typical error (%) 3.6 887 1780 C0.13 4.1 1000 1430 0.26 4.2 1020 1370 C0.34 7.2 1780 887 0.16 8.2 2000 825 0.14 8.4 2100 845 C0.50 programming the charge current the current-error amp ( c-ea) measures the current through an internal 0.3 current sense resistor between the chgsns and bat pins . the c-ea outputs a fraction of the charge current, 1/h prog , to the prog pin. the voltage-error amp (v-ea) and pwm control circuitry can limit the prog pin voltage to control charge current. an internal clamp (dz) limits the prog pin voltage to v prog , which in turn limits the charge current to: i chg = h prog ? v prog r prog = 1212v r prog i chg _ trkl = 120v r prog where h prog is typically 988 , v prog is either 1.227v or 122mv during trickle charge, and r prog is the resistance of the grounded resistor applied to the prog pin. the prog resistor sets the maximum charge current, or the current delivered while the charger is operating in constant-current (cc) mode. analog charge current monitor the prog pin provides a voltage signal proportional to the actual charge current. care must be exercised in measuring this voltage as any capacitance at the prog pin forms a pole that may cause loop instability. if observing the prog pin voltage, add a series resistor of at least 2k and limit stray capacitance at this node to less than 50pf. in the event that the input voltage cannot support the demanded charge current , the prog pin voltage may not represent the actual charge current. in cases such as this, the pwm switch frequency drops as the charger enters dropout operation where the top switch remains on for more than one clock cycle as the inductor current attempts to ramp up to the desired current. if the top switch remains on in dropout for 8 clock cycles a dropout detector forces the bottom switch on for the remainder of the 8th cycle. in such a case, the prog pin voltage remains at 1.227v, but the charge current may not reach the desired level. ntc thermal battery protection the ltc4121 monitors battery temperature using a therm - istor during the charging cycle . if the battery temperature moves outside a safe charging range, the ic suspends charging and signals a fault condition until the tempera - figure 6. ntc connection 4121 f06 bat too cold r bias 74% intv cc r adj opt li-ion + intv cc ntc r ntc t ltc4121 + ? too hot 37% intv cc + ? ignore ntc 2% intv cc + ? lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
15 o pera t ion ture returns to the safe charging range. the safe charging range is determined by two comparators that monitor the voltage at the ntc pin. ntc qualified charging is disabled if the ntc pin is pulled below about 85mv (v dis ). thermistor manufacturers usually include either a tem - perature lookup table identified with a characteristic curve number , or a formula relating temperature to the resistor value. each thermistor is also typically designated by a thermistor gain value b25/85. the ntc pin should be connected to a voltage divider from intv cc to gnd as shown in figure 6. in the simple application (r adj = 0) a 1% resistor, r bias , with a value equal to the resistance of the thermistor at 25c is con - nected from intv cc to ntc, and a thermistor is connected from ntc to gnd. with this setup, the ltc4121 pauses charging when the resistance of the thermistor increases to 285% the r bias resistor as the temperature drops. for a vishay curve 2 thermistor with b25/85 = 3490 and 25c resistance of 10k, this corresponds to a temperature of about 0 c. the ltc4121 also pauses charging if the thermistor resistance decreases to 58.8% of the r bias resistor. for the same vishay curve 2 thermistor, this corresponds to approximately 40c. with a vishay curve 2 thermistor, the hot and cold comparators both have about 2c of hysteresis to prevent oscillations about the trip points. the ntc comparator trip points are ratio metric to the intv cc voltage, so ntc trip points are defined as a percentage of intv cc . the hot threshold is calculated as 285%/385% = 74 % of intv cc and the cold threshold is calculated as 58.8%/158% = 37% of intv cc . the hot and cold trip points may be adjusted using a differ - ent type of thermistor, or a different r bias resistor, or by adding a desensitizing resistor , r adj , or by a combination of these measures as shown in figure 6 . for example, by increasing r bias to 12.4k, with the same thermistor as before, the cold trip point moves down to C5c, and the hot trip point moves down to 34c. if a vishay curve 1 thermistor with b25/85 = 3964 and resistance of 100k at 25 c is used, a 1% r bias resistor of 118k and a 1% r adj resistor of 12.1k results in a cold trip point of 0c, and a hot trip point of 39c. end-of-charge indication and safety timeout the ltc4121 uses a safety timer to terminate charging. whenever the ltc4121 is in constant current mode the timer is paused , and when fb rises or falls through the v rchg threshold the timer is reset. when the battery voltage reaches the float voltage, the safety timer begins counting down a 2-hour timeout. if charge current falls below one tenth of the programmed maximum charge cur - rent ( h c/10 ), the chrg status pin rises, but top-off charge current continues to flow until the timer finishes. after the timeout, the ltc4121 enters a low-power sleep mode. automatic recharge in sleep mode, the ic continues to monitor battery voltage. if the battery falls 2 .2% (v rchg or v rchg_42 ) from the full- charge float voltage, the ltc4121 engages an automatic recharge cycle as the safety timer is reset. automatic recharge has a built in delay of about 0.5ms to prevent triggering a new charge cycle if a load transient causes the battery voltage to drop temporarily. state of charge and fault status pins the ltc4121 contains two open-drain outputs which provide charge status and signal fault indications. the chrg pin pulls low to indicate charging at a rate higher than c/10. the fault pin pulls low to indicate a bad bat - tery timeout , or to indicate an ntc thermal fault condition. during ntc faults the chrg pin remains low, but when a bad-battery timeout occurs the chrg pin de-asserts. when the open drain outputs are pulled up with a resistor , table 3 summarizes the charger state that is indicated by the pin voltages. table 3 ltc4121 open-drain indicators with resistor pull-ups fault chrg charger state high high off or topping-off charge at a rate less than c/10. high low charging at rate higher than c/10 low high bad battery fault low low ntc thermal fault, charging paused low battery voltage operation the ltc4121 automatically preconditions heavily dis - charged batteries. if the battery voltage is below v lowbat minus its hysteresis (typically 2.05v - e.g. battery pack lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
16 protection has been engaged) a dc current, i lowbat , is applied to the bat pin from the intv cc supply. when the battery voltage rises above v lowbat , the switching regulator is enabled and charges the battery at a trickle charge level of 10% of the full scale charge current (in addition to the dc i lowbat current). trickle charging of the battery continues until the sensed battery voltage rises above the trickle charge threshold , v trkl , or v trkl_42 . when the battery rises above the trickle charge threshold the full scale charge current is applied and the dc trickle charge current is turned off. if the battery remains below the trickle charge threshold for more than 30 minutes, charging terminates and the fault status pin is asserted to indicate a bad battery . after a bad battery fault, the ltc4121 automatically restarts a new charge cycle once the failed battery is removed and replaced with another battery. the ltc4121-4. 2 monitors the batsns pin volt - age to sense lowbat and trkl conditions. precision run /shutdown control the ltc4121 remains in a low power disabled mode until the run pin is driven above v en (typically 2.45v). while the ltc4121 is in disabled mode, current drain from the battery is reduced to extend battery lifetime , the status pins are both de-asserted, and the fbg pin is high impedance. charging can be stopped at any time by pulling the run pin below 2.25v. the ltc4121 also offers an extremely low operating current shutdown mode when the run pin is pulled below v sd ( typically about 0.7v). in this condition less than 20a is pulled from the supply at in. tie the run pin to a resistive divider from the in supply to program the voltage where the ltc4121 turns on. examples are shown in figures 9 and 10. differential under voltage lockout the ltc4121 monitors the difference between the battery voltage, v bat , and the input supply voltage, v in . if the difference (v in C v bat ) falls to ?v duvlo , all functions are disabled and the part is forced into shutdown mode until (v in C v bat ) rises above the ?v duvlo rising threshold. the ltc4121-4. 2 monitors the v batsns and v in pin voltages to sense duvlo condition. o pera t ion user selectable switching regulator operating frequency the ltc4121 uses a constant-frequency synchronous step-down switching regulator architecture to pro - duce high operating efficiency. the nominal operating frequency, f osc , is programmed by pulling the freq pin to either intv cc or to gnd to obtain a switching frequency of 1.5mhz or 750khz, respectively. the high operating frequency allows the use of smaller external components. selection of the operating frequency is a trade-off between efficiency, component size, and margin from the minimum on-time of the switcher. operation at lower frequency improves efficiency by reducing internal gate charge and switching losses, but requires larger inductance values to maintain low output ripple . operation at higher frequency allows the use of smaller components, but may require sufficient margin from the minimum on-time at the lowest duty cycle if fixed-frequency switching is required. pwm dropout detector if the input voltage approaches the battery voltage , the ltc4121 may require duty cycles approaching 100%. this mode of operation is known as dropout . in dropout, the operating frequency may fall well below the programmed f osc value. if the top switch remains on for eight clock cycles, the dropout detector activates and forces the bottom switch on for the remainder of that clock cycle or until the inductor current decays to zero. this avoids a potential source of audible noise when using ceramic input or output capacitors and prevents the boost sup - ply capacitor for the top gate drive from discharging. in dropout operation, the actual charge current may not be able to reach the full-scale programmed value. in such a scenario the analog charge current monitor function does not represent actual charge current being delivered. burst mode ? operation at low charge currents, for example during constant- voltage mode, the ltc4121 automatically enters burst mode operation . in burst mode operation the switcher is periodically forced into standby mode in order to improve lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
17 o pera t ion efficiency. the ltc4121 automatically enters burst mode operation after it exits constant-current (cc) mode and as the charge current drops below about 80ma. burst mode operation is triggered at lower currents for larger prog resistors, and depends on the input supply voltage, the battery voltage , and the selected inductor. refer to the burst mode trigger current and typical burst mode waveforms graphs in the typical performance characteristics section for more information on burst mode operation. burst mode operation has some hysteresis and remains engaged for battery current up to about 150ma, depending on l sw ,v in and v bat . when operating in burst mode, the prog pin voltage to average charge current relationship is not well defined. this may cause the chrg pin to de-assert early depending on the amplitude of the burst ripple. boost supply refresh the boost supply for the top gate drive in the ltc4121 switching regulator is generated by bootstrapping the boost flying capacitor to intv cc whenever the bottom switch is turned on. this technique provides a voltage of intv cc from the boost pin to the sw pin. in the event that the bottom switch remains off for a prolonged period of time, e.g. during burst mode operation, the boost supply may require a refresh. similar to the pwm dropout timer, the ltc4121 counts the number of clock cycles since the last boost refresh. when this count reaches 32 the next pwm cycle begins by turning on the bottom side switch first. this pulse refreshes the boost flying capacitor to intv cc and ensures that the top-side gate driver has sufficient voltage to turn on the top side switch at the beginning of the next cycle. operation without an input supply or shaded panel when a battery is the only available power source , care should be taken to eliminate loading of the in pin. load current on in drains the battery voltage through the body diode of the top side power switch as v in falls below v sw . a diode inserted in series with the solar panel , as shown on the front page schematic, eliminates this discharge path. alternatively, a diode may be placed in series with the bat pin (as shown in figure 8). lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
18 a pplica t ions i n f or m a t ion mppt programming the maximum power-point tracking loop is programmed by selecting a resistive divider from in to mppt to gnd as shown in figure 4. this user programmable voltage divider (k r ) serves to define a fraction of the input voltage that appears at the mppt pin: k r = r mppt2 r mppt1 + r mppt2 = v mppt v in this fraction of v in is continuously compared against a fixed fraction of the open-circuit input voltage that is stored within the ltc4121. a fixed internal resistive divider (0.1 ? v in ) is periodically sampled to compare the open- circuit input voltage against the user defined fraction of the loaded input voltage (k r ? v in ). on an interval of t mp , the ltc4121 turns off all charger functions reverting to standby mode . the ltc4121 then waits for a delay, of about 36ms, pw mp , after turning off the charge current to allow the input supply to recover to its open-circuit volt - age. finally, the ltc4121 samples the open-circuit input voltage v oc through a fixed internal divider; k f = 1/10. after sampling the open-circuit voltage , the ltc4121 turns on all functions and reverts to normal operation . during normal operation, the stored 0.1 ? v oc voltage is compared against the instantaneous mppt pin voltage : k r ? v in . if the mppt voltage falls below the stored level , the charge current is reduced to maintain the input voltage. the ratio of 0.1/k r defines the percentage below the open-circuit voltage where charge current is reduced to maintain the maximum input power. because mppt operation involves large changes of input voltage, it is important to ensure that the programmed maximum power voltage does not violate minimum input operating conditions : 4.4v or 160mv above the battery voltage, whichever is higher. for example , to select an mppt set point, v mp , at 75% of the open-circuit voltage , v oc , select ratio k r using the following relation: k r = k f 75% = 0.1 0.75 = 0.1333 using the schematic of figure 4, this ratio is obtained by selecting: r mppt1 = 1 ? k f 75% ? ? ? ? ? ? k f 75% ? ? ? ? ? ? ? r mppt2 r mppt1 = 6.5 ? r mppt2 using standard 1% resistors, this is obtained with: r mppt1 = 787k and r mppt2 = 121k. mppt error terms uncertainty in programming the mppt set point is bound by three error terms : mppt pin leakage, dac quantization error, and the finite offset error in the mppt error amp. all error terms are lumped into v mp(os) , with a typical value of C45mv. this offset at the input to the mppt error amp is multiplied by 1/k r when observed at the in regulation point, v mp . for example, with the same k r = 0 .1333 (r mppt1 = 787k and r mppt2 = 121k) the C45mv v mp(os) error gets am - plified to C45mv/0.1333 = C338mv at v in from the v mp set point of 75 % of v oc . if v oc is 30v, the minimum v mp regulation point is about 22.16v, or 73.9% of the open- circuit voltage. for solar panel sources , the available power drops off quickly on the high side , and relatively slowly on the low side, this is illustrated in the curve in figure 7. for these types of sources , it is usually better to err on the low side when programming the v mp voltage . this is what the ltc4121 does normally, so most users can simply design for a v mp voltage at ( or just below) the level specified by the solar panel manufacturer. for more information on solar panels, refer to the panels data sheet. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
19 figure 7. typical 3w panel power vs voltage panel voltage (v) 0 power (w) 2 3 4 15 25 4121 f07 1 0 5 10 20 75c 50c 25c a pplica t ions i n f or m a t ion the maximum input voltage allowed to maintain constant frequency operation is: v in(max) = v lowbat f osc ? t min(on) where v lowbat , is the lowest battery voltage where the switcher is enabled. exceeding the minimum on-time constraint does not affect charge current or battery float voltage , so it may not be of critical importance in most cases and high switching frequencies may be used in the design without any fear of severe consequences. as the sections on inductor selection and capacitor selection show, high switching frequencies allow the use of smaller board components , thus reducing the footprint of the applications circuit. fixed-frequency operation may also be influenced by dropout and burst mode operation as discussed previously. switching inductor selection the primary criterion for switching inductor value selection in an ltc4121 charger is the ripple current created in that inductor. once the inductance value is determined, the saturation current rating for that inductor must be equal to or exceed the maximum peak current in the inductor, i l(peak) . the peak value of the inductor current is the sum of the programmed charge current , i chg , plus one half of the ripple current , ?i l . the peak inductor current must also remain below the current limit of the ltc4121, i peak . i l(peak) = i chg + ? i l 2 < i peak the current limit of the ltc4121, i peak , is at least 585ma (and at most 1250ma). the typical value of i peak is illus- trated in a graph in the typical performance characteristics , r sns current limit vs temperature. input voltage and minimum on-time the ltc4121 maintains constant frequency operation un - der most operating conditions . u nder certain situations with high input voltage and high switching frequency selected and a low battery voltage , the ltc4121 may not be able to maintain constant frequency operation. these factors, combined with the minimum on-time of the ltc4121, impose a minimum limit on the duty cycle to maintain fixed-frequency operation. the on-time of the top switch is related to the duty cycle (v bat /v in ) and the switching frequency, f osc in hz: t on = v bat f osc ? v in when operating from a high input voltage with a low battery voltage , the pwm control algorithm may attempt to enforce a duty cycle which requires an on-time lower than the ltc4121 minimum, t min(on) . this minimum duty cycle is approximately 18% for 1.5mhz operation or 9% for 750khz operation. if this occurs, the charge current and battery voltage remains in regulation , but the switching duty cycle may not remain fixed, or the switch - ing frequency may decreases to an integer fraction of its programmed value . lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
20 a pplica t ions i n f or m a t ion for a given input and battery voltage , the inductor value and switching frequency determines the peak-to-peak ripple current amplitude according to the following formula: ? i l = v in ? v bat ( ) ? v bat f osc ? v in ? l sw ripple current is typically set to be within a range of 20% to 40% of the programmed charge current, i chg . to obtain a ripple current in this range, select an inductor value us - ing the nearest standard inductance value available that obeys the following formula : l sw v in(max) ? v float ( ) ? v float f osc ? v in(max) ? 30% ? i chg ( ) then select an inductor with a saturation current rating greater than i l(peak) . input capacitor the ltc4121 charger is biased directly from the input supply at the v in pin. this supply provides large switched currents, so a high-quality, low esr decoupling capacitor is recommended to minimize voltage glitches at v in . bulk capacitance is a function of the desired input ripple voltage (?v in ), and follows the relation: c in(bulk) = i chg ? v bat v in ? v in (f) input ripple voltages (?v in ) above 0.01v are not recom - mended. 10 f is typically adequate for most charger applications, with a voltage rating of 40v. the input capacitor also forms a pole with the sour ce impedance that supplies power to v in . this r-c network must settle within the 36ms pw mp period for the ltc4121 to accurately sample the open-circuit voltage at v in . adequate settling is usually achieved in 3 to 5 r-c time constants. to allow the ltc4121 to correctly sample the open-circuit voltage, limit c in to: c in < pw mp / (5 ? r source ), where r source is the impedance of the power source . for a solar panel this is the impedance of the panel at the open-circuit voltage . looking at a panel' s i-v curve, the source impedance is approximated by (v oc C v mp )/i mp . typically v mp is about 80% of v oc , so the solar panels source impedance can be approximated as: r source v oc / (5 ? i mp ). reverse blocking when a fully charged battery is suddenly applied to the bat pin , a large in-rush current charges the c in capacitor through the body diode of the ltc4121 topside power switch. while the amplitude of this current can exceed several amps, the ltc4121 will survive provided the bat - tery voltage is below about 11v. to completely eliminate this in-rush current , a blocking p-channel mosfet should be placed in series with the bat pin . when the battery is the only source of power , this pmos also serves to de - crease battery drain current due to any load placed at v in , conducted through the body diode of the topside power switch on the ltc4121. the pmos body diode shown in figure? 8 serves as the blocking component since chrg is high impedance when the battery voltage is greater than the input voltage. when chrg pulls low, i.e. during most of a normal charge cycle, the pmos is on to reduce power dissipation. the pmos requires a forward current rating equal to the programmed charge current and a reverse breakdown voltage equal to the programmed float voltage. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
21 a pplica t ions i n f or m a t ion bat capacitor and output ripple: c b at the ltc4121 charger output requires bypass capacitance connected from bat to gnd (c bat ). a 22f ceramic ca - pacitor is required for all applications. in systems where the batter y can be disconnected from the charger output , additional bypass capacitance may be desired. in this type of application, excessive ripple and/or low amplitude oscillations can occur without additional output bulk capacitance. for optimum stability, the additional bulk capacitance should also have a small amount of esr. for these applications, place a 100f low esr non-ceramic capacitor ( chip tantalum or organic semiconductor capaci - tors such as sanyo os-cons or poscaps) from bat to gnd, in parallel with the 22f ceramic bypass capacitor, or use large ceramic capacitors with an additional small series esr resistor of less than 1. this additional bypass capacitance may also be required in systems where the battery is connected to the charger with long wires . the voltage rating of all capacitors applied to c bat must meet or exceed the battery float voltage. boost supply capacitor the boost pin provides a bootstrapped supply rail that provides power to the top gate drivers. the operating volt - age of the boost pin is internally generated from intv cc whenever the sw pin pulls low. this provides a floating voltage of intv cc above sw that is held by a capacitor tied from boost to sw. a low esr ceramic capacitor of 10nf to 33nf is sufficient, with a voltage rating of 6v. intv cc supply and capacitor power for the top and bottom gate drivers and most other internal circuitry is derived from the intv cc pin. a low esr ceramic capacitor of 2.2f is required on the intv cc pin. the intv cc supply has a relatively low current limit (about 20ma) that is dialed back when intv cc is low to reduce power dissipation. do not use the intv cc voltage to supply power for any external circuitry except for the ntcbias network. when the run pin is above v en , the intv cc supply is enabled , and when intv cc rises above uv intvcc , the charger is enabled. figure 8. reverse blocking with a p-channel mosfet in series with the b at pin + + bat 22f 10f 4.7f 2.2f r prog r fb1 49.9k 4.99k 470k r fb2 li-ion fb fbg gnd chrg run intv cc v in v in ltc4121 si2343ds prog bat 22f 10f 4.7f 2.2f r prog 49.9k 470k li-ion batsns gnd chrg run intv cc v in v in ltc4121-4.2 sit2343ds prog 4121 f08 lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
22 calculating ic power dissipation the user should ensure that the maximum rated junction temperature is not exceeded under all operating conditions. the thermal resistance of the ltc4121 package ( ja ) is 54c/w; provided that the exposed pad is in good thermal contact with the pcb. the actual thermal resistance in the application will depend on the forced air cooling and other heat sinking means, especially the amount of copper on the pcb to which the ltc4121 is attached. the actual power dissipation while charging is approximated by the following formula: p d = v in ? v bat ( ) ? i trkl + v in ? i in(switching) + r sns ? i 2 chg + r dson(top) ? v bat v in ? ? ? ? ? ? ? i 2 chg + r dson(bot) ? 1 ? v bat v in ? ? ? ? ? ? ? i 2 chg during trickle charge (v bat < v trkl ) the power dissipation may be significant as i trkl is typically 10ma, however during normal charging the i trkl term is zero. i trkl is also zero if v bat approaches intv cc , since i trkl is sourced from the intv cc ldo. the junction temperature can be estimated using the fol - lowing formula: t j = t a + p d ? ja . where t a is the ambient operating temperature. a pplica t ions i n f or m a t ion pcb layout to prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the ltc4121 is essential. for maximum efficiency , the switch node rise and fall times should be minimized. the following pcb design priority list will help insure proper topology . layout the pcb using the guidelines listed below in this specific order: 1. v in input capacitor should be placed as close as possible to the in pin with the shortest copper traces possible. the ground return of the input capacitor should be connected to a solid ground plane. 2. place the inductor as close as possible to the sw pin. minimize the surface area of the sw pin node . make the trace width the minimum needed to support the programmed charge current, and ensure that the spacing to other copper traces be maximized to reduce capacitance from the sw node to any other node. 3. place the ba t capacitor adjacent to the bat pin and ensure that the ground return feeds to the solid ground plane. 4. ro ute analog ground ( run pin divider grounded resistor , the mppt pin divider , and intv cc capacitor ground ) to the solid ground plane. 5. it is important to minimize parasitic capacitance on the prog pin. the trace connecting to this pin should be as short as possible with extra wide spacing from adjacent copper traces. 6. keep the gnd capacitance of the mppt pin to a mini - mum, and reduce coupling from the mppt pin to any of the switching pins (sw, boost, and chgsns) by routing the mppt trace away from these signals. maximize the copper area connected to the exposed pad. place via connections directly under the exposed pad to connect a large copper ground plane to the ltc4121 to improve heat transfer. example pcb layout files of the ltc4121 are available at the following link: http://www.linear.com/product/ltc4121#demoboards. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
23 a pplica t ions e xa m ples design example 1 consider the design example, shown in figure 14 on the last page, for the ltc4121-4.2. input power is from a solar panel that has an open-circuit voltage v oc = 21.6v, and maximum power voltage v mp = 17v, or 79% of the open-circuit voltage . the battery float voltage is 4.2v, and the desired charge current is 400ma. the application has a minimum battery voltage of 2.5v. there is no requirement given for the input voltage where the ltc4121-4. 2 should turn on. given that the mppt set point, v mp , is at 79% of the open-circuit voltage of 21.6v, one may elect to turn-on the ltc4121-4.2 at an input voltage anywhere below this set point. a level of 60% of the open-circuit voltage is selected , or 13v. this selection results in a run pin divider of r run1 = 464k, and r run2 = 107k. with this run pin divider, the ltc4121-4.2 en - ters disabled mode if the input supply drops below 12v. now select the mpp t resistive divider to obtain a maxi - mum power point of 17v. the maximum power point of 17v is at 79 % of the open-circuit voltage. this is used to calculate the ratio v mp v oc = 0.1 k r select k r = 0.1/0.79 = 0.1266 this ratio is obtained by selecting r mppt1 and r mppt2 following: r mppt1 = (1 ? 0.1266) 0.1266 r mppt2 = 6.9 ? r mppt2 using standard 1% resistors, select r mppt1 = 698k and r mppt2 = 100k to obtain a k r of 0.1253, and an mppt set point of 17.24v. as described in the mppt error terms section , the actual regulation voltage will vary from the programmed voltage down to 45mv /k r = 359mv below the programmed voltage. in this example, the expected regulation voltage is 16.88v to 17.24v, or 78.2% to 80.1% of the open-circuit voltage. the switching frequency of 750khz is selected to achieve an on-time of 154ns which is greater than t min(on) at the maximum input supply, and minimum battery voltage of 2.5v. t on = 2.5v 750khz ? 21.6v = 154.3 > t min(on) next, the minimum standard inductance value is found that maintains an inductor ripple current 30% of i chg , at the peak power input voltage of 17v using the following formula: l sw > (17v ? 4.2v) ? 4.2v 750khz ? 17v ? (30% ? 400ma) = 35h the next largest standard inductance value is 47h. this inductor selection results in a ripple current of 90ma and peak inductor current i l(peak) of: i l(peak) = 400ma + (17v ? 4.2v) ? 4.2v 2 ? 750khz ? 17v ? 47h i l(peak) = 444ma the saturation current of the switch inductor needs to be greater than i l(peak) . now select r prog for the desired average charge current during constant-current operation . the nearest standard 1% resistor to satisfy the following relation: r prog = h prog ? 1.227v 400ma = 3.01k ? select c in = 10f for the input decoupling capacitor, achieving an input voltage ripple of 10mv. ? v in = 400ma ? 4.2v 17v 10f = 10mv the minimum standard voltage rating for c in is 50v. select c intvcc = 2.2f, and c bst = 22nf, and finally the battery capacitor should be 22f. the lowest standard voltage rating for these capacitors is 6v. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
24 a pplica t ions e xa m ples in this design example, maximum power dissipation is calculated during trickle charge as: p d = (17v ? 2.5v) ? 10ma + 17v ? 2.5ma + 0.3 ? ? 0.04a 2 + 0.8 ? ? 4.2v 17v 0.04a 2 + 0.5 ? ? 1 ? 2.5v 17v ? ? ? ? ? ? ? 0.04a 2 = 0.19w this dissipated power results in a junction temperature rise of: p d ? ja = 0.19w ? 54c/w = 10.2c estimating i in(switching) at 2.5ma from the i in(switching) current vs input voltage graph at v in = 17v, during regular charging with v bat > v trkl , the power dissipation reduces to: p d = 17v ? 2.5ma + 0.3 ? ? 0.4a 2 + 0.8 ? ? 4.2v 17v 0.4a 2 + 0.5 ? ? 1 ? 4.2v 17v ? ? ? ? ? ? ? 0.4a 2 = 0.18w this dissipated power results in a junction temperature rise of 9.8c over ambient. design example 2 consider the design with a 3.5w or greater solar panel with a maximum input voltage of v oc = 22.4v and a maximum power voltage of v mp = 18v or 80.3% of the open-circuit voltage. the minimum battery voltage is 5v, and the float voltage is 8.2v, with a charge current of 400ma. the mppt set point is at 80 .3% of the open-circuit volt - age. so select k r = 0.1/0.803 = 0.1245 this ratio is obtained by selecting r mppt1 and r mppt2 following: r mppt1 = (1 ? 0.1245) 0.1245 r mppt2 = 7.03 ? r mppt2 using standard 1% resistors, select r mppt1 = 715k and r mppt2 = 102k to obtain a k r of 0 . 1248 and nominal mppt set point of 17.94v. including the effect of mppt error terms, the expected mppt regulation voltage will vary between 17.58v to 17.94v or 78.5% to 80.1% of the open-circuit voltage. next, the external feedback divider, r fb1 /r fb2 , is found using standard 1% values listed in table 2. r fb1 = 2.05m r fb2 = 845k with these resistors, and including the resistance of the fbg pin, the battery float voltage is 8.22v. select the run pin divider to turn on the charger when the solar-cell output reaches 14.7v. this is obtained by selecting r run1 = 536k, and r run2 = 107k. this selec- tion turns off the charger if the input falls below 13.52v. the sw itching frequency is selected at 1. 5mhz which meets the minimum on-time requirement for battery voltages as low as 5v. t on = 5v 1.5mhz ? 17.94v = 186ns > t min(on) the minimum standard inductance value for a 30% ripple current is l sw > (17.94v ? 8.2v) ? 8.2v 1.5mhz ? 17.94v ? (30% ? 400ma) = 24.8h the nearest standard inductor value greater than this is 33h. with an inductor of 33h, the peak inductor current is 445ma and the ripple current amplitude , ?i l , is 90ma. select an inductor with a saturation current greater than the peak inductor current. select r prog = 3.01k, as the nearest standard 1% value to provide a charge current of 403ma during constant- current operation. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
25 select a 50v rated capacitor for c in = 10f to achieve an input voltage ripple of 10mv. and select 6v rated capaci - tors for c intvcc = 2.2f, c boost = 22nf, and a 10v rated c bat = 22f. due to the large float voltage diode d7 is placed in series with the bat pin to prevent exceeding the abs max cur - rent rating on the r sns resistor in the event that a fully charged battery may be connected. in this design example, maximum power dissipation is calculated during trickle charge with the following as - sumptions: v bat = 5.7v, v in is 19v, and i in(switching) is estimated from the i in(switching) current vs input voltage graph in the typical performance characteristics section at v in = 19v and freq = intv cc as 4ma. p d = 19v ? 4ma + 0.3 ? ? 0.04a 2 + 0.8 ? ? 5.7v 19v 0.04a 2 + 0.5 ? ? 1 ? 5.7v 19v ? ? ? ? ? ? ? 0.04a 2 = 77mw a pplica t ions e xa m ples this dissipated power results in a junction temperature rise of: p d ? ja = 0.077w ? 54c/w = 4.2c during regular charging with v bat = 8.2v, and assuming v in is at the mppt voltage of 17.94v, the power dissipa - tion increases to: p d = 18v ? 4ma + 0.3 ? ? 0.4a 2 + 0.8 ? ? 8.2v 19v 0.4a 2 + 0.5 ? ? 1 ? 8.2v 19v ? ? ? ? ? ? ? 0.4a 2 = 0.22w this dissipated power results in a junction temperature rise of 12c over ambient. intv cc freq boost sw chgsns bat fb fbg ntc in run mppt chrg fault ltc4121 bat54 gnd 470k 470k r run1 536k c in 10f + r run2 107k r mppt2 102k in in r mppt1 715k + + r fb1 2.05m r fb2 845k c bst 22nf l sw 33h 10k t prog + c bat 22f 4121 f09 li-ion t = nths0805n02n1002f r prog 3.01k c intvcc 2.2f v oc = 22.4v, v mp = 18v intv cc v float = 8.2v figure 9. design example 2 with ltc4121 lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
26 a pplica t ions e xa m ples design example 3 consider the design of a sealed lead acid charger with temperature compensation of the float voltage. sealed lead acid batteries require the float voltage be decreased as cell temperature rises. with the ltc4121 this is achieved using an ntc thermistor in the feedback pin divider as shown in figure 10. using the circuit of figure 10 above , the float voltage automatically decreases with temperature as shown in figure 11. the ntc pin is grounded in this example to figure 10. design example 3, sla charging with ltc4121 disable ntc qualified charging and highlight the float volt - age programming over a wide temperature range . with an ntc pin network connected , as in example 1 or example 4, the charger would be disabled below 0c or above 40c. the sealed lead acid charger of example 3 is configured to charge from a variable supply that can range from 6.2v up to 40v. the switch frequency is selected at 750khz to meet minimum on time requirements at v bat = 4.2v. and a 47h switch inductor is selected to keep ripple current below 30% of i chg at v in = 40v. figure 11. sealed lead acid float voltage intv cc boost sw chgsns bat fb fbg in run mppt ntc freq ltc4121 gnd c in 10f v in r mppt1 10k r fb1a 102k r fb1b 464k c bst 22nf l sw 47h r fb2 698k r t1 100k r fb1c 866k c ff 1nf prog + c bat 22f 4121 f10 sla r t1 = nths0402e3104fht r prog 3.01k c intvcc 2.2f intv cc v float = 6v + ? temperature (c) ?40 5.0 v float (v) 6.6 6.4 6.2 6.0 5.6 5.8 5.2 5.4 7.0 6.8 ?25 ?10 205 35 4121 f11 50 95 110 65 80 125 ntc = gnd lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
27 figure 12. design example 4, ltc4121 2-cell li-ion charger with mppt tracking for a resistive supply figure 13. v mp /v oc and i b at vs v in(oc) a pplica t ions e xa m ples design example 4 consider the design of a li-ion charger from a resistive supply. with a resistive supply voltage, the maximum power point is at 50% of the open-circuit voltage. program a 50% peak power point using k r = 0.199 with r mppt1 = 332k and r mppt2 = 82.5k. this network keeps the input voltage at the peak power point for any input resistance so long as the r-c time constant of r in ? c in does not exceed pw mp /5, here c in is 22f. with 100? of source impedance, the input voltage regu - lation loop holds the ratio of (v mp /v in ) at about 49% for v in ranging from 9v up to 28.3v. for lower input voltages than 8.7v, the mppt set point is below duvlo when v bat = 4.2v. and above 28.3v, the charger attains the full programmed charge current of 400ma so mppt regula - tion lets go. while the ltc4121 regulates v in , the battery charge current is automatically scaled to track available input power. figure 13 illustrates the circuit performance measured with v bat held at 4.0v, showing the ratio of v mp /v oc and i bat versus v oc with r in = 100? in series with the supply. l sw is sized to maintain ripple current below 30 % of i chg at v in = 16v. the fb pin network is programmed to set v float = 4.2v. an ntc network is configured to enable charging when the battery temperature is between 0 c and 40c. intv cc boost sw chgsns bat fb fbg ntc in run mppt ltc4121 gnd c in 22f r mppt2 82.5k r in r mppt1 332k + ? r fb1 1.01m r fb2 1.35m c bst 22nf l sw 33h freq prog + c bat 22f 4121 f12 t = ntcs0402e3103fht r prog 3.01k t 10k li-ion c intvcc 2.2f v mp intv cc v float = 4.2v v in v in(oc) (v) 5 10 v mp / v oc (%) i bat (ma) 40 30 60 50 20 100 80 70 90 0 150 100 250 200 50 450 350 300 400 10 4121 f13 15 20 25 30 35 40 v bat = 4v r in = 100 lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
28 p ackage descrip t ion ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691 rev ?) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691 rev ?) lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
29 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . r evision h is t ory rev date description page number a 05/15 clarified device options clarified note 4 modified end-of-charge indication section enhanced reverse blocking section modified related parts list 1 5 15 20-21 28 lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121
30 ? linear technology corporation 2014 lt 0515 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4121 r ela t e d p ar t s typical a pplica t ion figure 14. design example 1 with ltc4121-4.2 intv cc boost sw chgsns bat batsns ntc in run mppt ltc4121-4.2 chrg fault gnd 470k 470k r run1 464k c in 10f + r run2 107k 10k r mppt1 698k r mppt1 100k c intvcc 2.2f + + c bst 22nf l sw 47h freq prog 4121 ta02 v oc = 21.6v, v mp = 17v intv cc c bat 22f v float = 4.2v t + li-ion t = nths0805n02n1002f r prog 3.01k part number description comments lt ? 3650-8.2/ lt3650-8.4 monolithic 2a switch mode non-synchronous 2-cell li-ion batter y charger standalone 9v < v in < 32v (40v absolute maximum), 1mhz, 2a programmable charge current, timer or c/10 termination, small and few external components 3mm 3mm dfn-12 package -8.2 for 2 4.1v float voltage batteries, -8.4 for 2 4.2v float voltage batteries. lt3650-4.1/ lt3650-4.2 monolithic 2a switch mode non-synchronous 1-cell li-ion batter y charger standalone 4.75v < v in < 32v (40v absolute maximum), 1mhz, 2a programmable charge current, timer or c/10 termination, small and few external components 3mm 3mm dfn-12 package -4.1 for 4.1v float voltage batteries, -4.2 for 4.2v float voltage batteries. lt3652hv power tracking 2a battery charger input supply voltage regulation loop for peak power tracking in (mppt) solar applications, 4.95v < v in < 34v (40v absolute maximum), 1mhz, 2a charge current, 3.3v < v out < 18v. timer or c/10 termination, 3mm 3mm dfn-12 package and msop-12 packages. lt c4070 li-ion/polymer shunt batter y charger system low operating current (450na), 1% float voltage accuracy over full temperature and shunt current range, 50ma maximum internal shunt current (500ma with external pfet), pin selectable float voltages: 4.0v, 4.1v, 4.2v. ultralow power pulsed ntc float conditioning for li-ion/polymer protection, 8-lead (2mm 3mm) dfn & msop. ltc4071 li-ion/polymer shunt battery charger system with low battery disconnect integrated pack protection, < 10na low battery disconnect protects battery from over-discharge. low operating current (550na), 1% float voltage accuracy over full t emperature and shunt current range, 50ma maximum internal shunt current, pin selectable float v oltages: 4.0v, 4.1v, 4.2v. ultralow power pulsed ntc float conditioning for li-ion/ polymer protection, 8-lead (2mm 3mm) dfn and msop. ltc4065/ ltc4065a standalone li-ion battery charger in 2mm 2mm dfn 4.2v 0.6% float voltage, up to 750ma charge current; a version has /acpr function. 2mm 2mm dfn package. lt c4079 60v 250ma multi-chemistry linear battery charger 2.7v C 60v input voltage range, 1.2v C 60v adjustable battery voltage range and 10ma C 250ma charge current range. low 4a quiescent current. input voltage and thermal regulation. 10-pin 3mm x 3mm dfn package. lt c4121/lt c4121-4.2 4121fa for more information www.linear.com/ltc4121

▲Up To Search▲

Price & Availability of LTC4121-42-15

	To Download LTC4121-42-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .